=== Frequency translators ===

2335 Loop test translator (Ku-band to L-band) replaces the satellite link during system tests. Fin =14.0-14.5 GHz, Fout =950-1450 MHz, F(LO) =13.05 GHz, F Stab =50 kHz over 0+50C, Pin =+20 dBm, P1dB(in) =+15 dBm, Att(in) >30 dB, Imp =50 Ohm, LO Harm =-20 dBc, LO Spur =-80 dBc, LO PhN =-90 dBc/Hz (10 kHz), (SMA), 0+50C
2336 Loop test translator (C-band) replaces the satellite link during system tests. Fin =5.850-6.425 GHz, Fout =3.625-4.200, F(LO) =2.225 GHz, F Stab =10 kHz over 0+50C, overall CL =20 dB, Pin =+20 dBm, P1dB(in) =+7 dBm, Att(in) >30 dB, Imp =50 Ohm, LO Harm =-20 dBc, LO Spur =-80 dBc, LO PhN =-90 dBc/Hz (10 kHz), SMA, 0+50C
2337 Loop test translator (S-band) replaces the satellite link during system tests. Fin =2025-2125 MHz, Fout =2.2-2.3 GHz, F(LO) =175 MHz, F Stab =5 kHz over 0+50C, overall CL =20 dB, Pin =+20 dBm, P1dB(in) =+7 dBm, Att(in) >30 dB, Imp =50 OHm, LO Harm =-20 dBc, LO Spur =-80 dBc, LO PhN =-90 dBc/Hz (10 kHz), SMA, 0+50C
2697 Receiver/translator, 4/8 channel, wideband, cellular band, Fin =824 -894 MHz, Fout =1.5-11.5 MHz, BW =10 MHz, NF =7 dB, Gn =60 dB, T(Synth Tun) =100 ms, Synth step =5 MHz, Synth PhN =-110 dBc/Hz (>1 kHz), instantaneous DynR >80 dB, image/RF Rej >80 dB, RF Gn control =30 dB in 2 dB steps
2698 Receiver/translator, VHF/UHF, 5 channel wideband, Fin =20-1200 MHz, Fout =1.5-11.5 MHz, BW =10 MHz, Gn =65 dB, T(Synth Tun) <50 ms, Synth step =5 MHz, image/IF Rej >80 dB, RF Gn control =30 dB in 2 dB steps
7506 Frequency translator, synthesized clock, ensure a phase stable output clock and smooth transition between Master and Slave operation. In the Slave mode the output frequency phase locks to the input clock while in the Master mode the output signal is derived from an internally stable OCXO. For FEC clock encoder/decoder for 10 Gbit/s and up, SONET/SDH/DSL-PON timing. Clock signal (I/O): PECL, output symmetry =50%, jitter =0.25 ps (rms), input Fr variation = 20 ppm, jitter transfer <0,05 dB, Fin =8.192 to 2488 MHz, Fout=8.192 to 2488 MHz, supply voltage = +5 & +8 V @ I=600 & 50 mA, size =6.0"x 40"x 0.62", -40 to +85C.
9877 Frequency translator. The IC is a voltage controlled SAW oscillator based clock generator PLL designed for clock frequency translation and jitter attenuation. The device supports both forward and inverse FEC (forward error correction) clock multiplication ratios. Multiplication rations are pin-selected from pre-programming look-up tables. Fin = 10-700 MHz, Fout = 100-700 MHz, SSB Ph N (@ Fin = 19.44 MHz) = -72 dBc/Hz(1 kHz), -94 dBc/Hz(10 kHz), -123 dBc/Hz(100 kHz), jitter (@ 622.08 MHz) = 0.5 ps rms, output duty cycle = 40-60 %, T(rise/fall) = 450 ps, supply voltage = 3.3 V @ I = 162 mA, size = 9x9 mm SMT
12957 Frequency translator, automatic phase slope limiting, dual differential inputs, input compatible with LVPECL, LVDS, HSTL, SSTL, etc, tunable loop filter response, two differential LVPECL outputs, small 9x9 mm SMT package. The IC integrates a high performance PLL with SAW VCO to provide a low jitter frequency translator. The internal high Q SAW filter provides low jitter signal performance and determines the output frequency of the SAW VCO. Fin=0.3-700 MHz, Fclc<50 MHz, F(Ref, clc)<200 MHz, Fout=77.76-700 MHz, SSB Ph N=-72 dBc/Hz (1 kHz), -94 dBc/Hz (10 kHz), -123 dBc/Hz (100 kHz), jitter=0.5 ps, duty cycle=50%, T (rise/fall)=450-275 ps, T(set-up)=5 ns, PLL lock time<100 ms, supply voltage=3.3 V@ I=162 mA
12958 Frequency translator, differential LLPECL outputs, tunable loop filter response, small 9x9 mm SMT package. The IC integrates a high performance PLL with SAW VCO to provide a low jitter frequency translator. The internal high Q SAW filter provides low jitter signal performance and determines the output frequency of the SAW VCO. A programmable output divider can divide the SAW VCO frequency by a factor of 4 to achieve an output as low as 77.76 MHz with a 311.04 MHz SAW VCO. The input to the frequency translator is provided by selecting between one of two input reference clocks. Fin=10-166 MHz, Fclc<50 MHz, Fout=77.75-667 MHz, SSB Ph N=-72 dBc/Hz (1 kHz), -94 dBc/Hz (10 kHz), -123 dBc/Hz (100 kHz), jitter=0.69 ps, duty cycle=50%, T(rise/fall)=450-275 ps, PLL lock time<1 ms, supply voltage=3.3 V@I=162 mA
12959 Frequency translator, differential LVPECL outputs, configurable loop and output dividers, tunable loop filter response, small 9x9 mm SMT package. The IC integrates a high performance PLL with SAW VCO to provide a low jitter frequency translator. The internal high Q SAW filter provides low jitter signal performance and determines the maximum output frequency of the SAW VCO. A programmable output divider can divide the SAW VCO frequency to achieve an output as low as 38.88 MHz. Fin=10-166 MHz, Fout=38.88-700 MHz, Fclc=50 MHz, Ph N=-72 dBc/Hz (1 kHz), -94 dBc/Hz (10 kHz), -123 dBc/Hz (100 kHz), jitter=0.69 ps, duty cycle=50%, T(rise/fall)=300-800 ps, PLL lock time=1 ms, supply voltage=3.3 V@ I=162 mA
12960 Frequency translator, integrated SAW delay line, small 9x9 mm SMT package includes SAW device, ideal for OC-48, SDH-12, 10 GbE transmit clock. The IC is a SAW VCO based clock generator PLL designed for reference clock frequency translation and jitter attenuation in a high speed data communications system. Fin=10-166 MHz, Fclc=50 MHz, Fout=77.75-667 MHz, SSB Ph N=-72 dBc/Hz (1 kHz), -94 dBc/Hz (10 kHz), -123 dBc/Hz (100 kHz), jitter=0.69 ps, duty cycle=50%, T(rise)=300-800 ps, T(set up)=5 ns, PLL clock time=1 ms, supply voltage=3.3 V@ I=162 mA
15449 Frequency translators (IF to IF) convert a 70 or 140 MHz signal to a 140 or 70 MHz IF with no spectrum inversion with low group delay and flat frequency response. Fin = 7018, 14018 MHz, Pin = -20-10 dBm, Imp (I/O) = 75 Ohm, Fout = 14018, 7018 MHz, Gn = 00.5 dB, Spurs < -45 dBc, Fr response = 0.3 dB @ 12 MHz, 0.5 dB @ 18 MHz, group delay < 3 ns @ 12 MHz, < 5 ns @ 18 MHz, Fr Acc < 1 kHz, Ph N <= -80 dBc/Hz (10 kHz), <= -90 dBc/Hz (100 kHz), <= -100 dBc/Hz (1 MHz), size = 19" x 1.75"x 14.0", Pcons < 30W.
16216 Clock translator, reconfigurable, single unit covers wide output and input frequency ranges, low jitter generation, PECL output, wide tracking range, single DC supply, miniature surface mount package, simple 2 wire serial programming. F=622-695 MHz (standard), 155-167, 622-667, 1244-1334, 2488-2668 MHz, other range 10-2700 MHz (options), Fin=2.5-200 MHz (standard), 100-1000, 500-2800, 1.5-100 MHz (options), translation ratio TR=N/D where N and D are integers, jitter generation<0.5 ps rms, Spurs<-60 dBc, Sens to ripple on DC<25 Hz/mV at 300 kHz, size=1?x1?x0.25?
18861 Frequency translator (I/Q modulator), high performance, MIC quadrature hybrid design, 6 bit TTL digital drive, low insertion loss. Frequency translator comprises fast switching digital shifters. The input binary word advances or retards the phase in discret increments. The device is switched periodically through 360 is increments that are equal to the least significant bit. The frequency translator converts the frequency of an RF carrier to a lower or higher frequency. F =2.25-3.75 GHz, translation loss =6 dB, carrier & sideband Supp =-30 dBc (at center frequency), -22 dBc (at ends of band), flatness =1.5 dB, VSWR =2.5, Pin =0.1 W (CW), T(switching) <30 ns, Fr translation =0-100 kHz, supply voltage =5 V @ 200 mA, SMA female connectors, -55 to +105C
20672 Loop test translators, available in L, C, X and Ku bands, low phase noise contribution, lock alarm indication. Options: higher frequency stability, input and output filtering, remote gain adjustment, external reference input, multiple frequency bands remote select, summary alarm. Fin/Fout=5850-6425/3625-4200, 5925-6425/950-1450, 14000-14500/12250-12750, 14000-14500/11700-12200, 14000-14500/10950-11450, 14000-14500/950-1450 MHz, Fr Stab=2 ppm(0.01 ppm optional), CL=18 dB, Gn Adj=30 dB, Gn flatness=1.5 dB@full band, 0.4 dB@40 MHz BW, RL(I/O)=15 dB, Ph N=-85 dBc/Hz (1 kHz), -95 dBc/Hz (10 kHz), -105 dBc/Hz (100 kHz), size=1.75''x19''x13'', +20 to +50C
21716 Loop test translators, simulates satellite link, high stability, low phase noise, gain adjustment, reference output, designed to replace the satellite link for test and alignment of earth station systems operating in S, C, X, Ku or DBS frequency bands. Incorporating fundamental frequency PLOs and double balanced mixers, the translators block convert frequencies from uplink to either downlink or L-band for instantaneous monitoring of frequency, power levels and modulation. Fin/Fout =2025-2125/2200-2300, 2025-2125/950-1050, 5845-6425/3620-4200, 5925-6425/950-1450, 5925-6425/1450-950, 7900-8400/7250-7750, 7900-8400/950-1450, 12750-13250/10950-11450, 12750-13250/10700-11200, 12750-13250/950-1450, 13750-14500/12000-12750, 13750-1450/11450-12200, 13750-14500/10950-11700, 13750-14500/10700-11450, 13750-14500/950-1700, 14000-14500/12250-12750, 14000-14500/11700-12200, 14000-14500/11450-11950, 14000-14500/10950-11450, 14000-14500/950-1450, 17300-17800/12200-12700, 17300-17800/12122-12622, 17300-17800/11700-12200, 17300-18100/11700-12500, 17800-18100/12200-12500, 18100-18400/10700-11000, 17300-17800/950-1450, 17300-18100/950-1750, 17300-18400/950-2050, 17800-18100/950-1250, 18100-18400/950-1250 MHz, Pin <+10 dBm, Conv Gn =-20 dB, Att range >30 dB, Imp =50 Ohm, VSWR (I/O) =1.8, F(Ref Int) =25 or 50 MHz, signal related Spurs =-50 dBc, LO related Spurs =-50 dBc, 0 to +50C
22752 Frequency translator accepts multiple input frequencies up to 170 MHz, low jitter PECL output, locked to specified input frequency, e.g. 8 kHz, lock/loss of signal alarm. Fout = 155.52-1200 MHz, T(rise/fall) =250 ps, duty cycle =49/51%, jitter =0.23 ps rms, input Fr tracking capability >40 ppm, supply voltage =5.0 or 3.3 V @ 75-45 mA, size =25.4x20.32x6.35 mm, 0 to +70C, -40 to +85C
22753 Frequency translator, AC/HCMOS compatible inputs and outputs, lock detect circuit surface mount option available, commercial or industrial or industrial temperature range, 19.44 MHz and 155.52 MHz clock outputs locked to an 8 kHz or 1.544 MHz input clock, jitter <10 ps rms at 19.44 MHz, 19 ps rms at 155.52 MHz, input Fr Tol =70 ppm, supply voltage =5.0 V
22754 Frequency translator, complete crystal-based, tri-state output allows board test, lock detect, 6-pin J-lead ceramic package (hermetic), CMOS output, clock smoothing, highly robust, reliable and predictable delive, used in communications applications where low jitter is paramount. Fout =0.1-77.76 MHz, Fin =0.001-77.76 MHz, T(rise/fall) =1.8 ns, duty cycle =45/55%, loop BW3 =10 Hz, jitter =4.7 ps rms, supply voltage =3.3 or 5.0 V @ 15-35 mA, size = 14.0x9.0x4.5 mm, 0 to +70C, -40 to +85C
22755 Frequency translator, crystal and SAW based, which are used to translate up to four input frequencies from 8 kHz to 170 MHz to any one specific output frequency from 1.024 to 1200 MHz. Applications: SONET/SDH, DWDM, FDM, ATM, DSL-PON interconnects
22756 Frequency translator, crystal-based, tri-state output allows board test, lock detect, clock smoothing, highly robust, reliable and predictable delive, used in communications applications where low jitter is paramount. Fout =0.1-77.76 MHz, Fin =0.001-77.76 MHz, T(rise/fall) =1.8 ns, duty cycle =45/55%, loop BW3 =10 Hz, jitter =4.7 ps rms, supply voltage =3.3 or 5.0 V @ 15-35 mA, size =5.0x7.5x2.0 mm, 0 to +70C, -40 to +85C
22757 Frequency translator, dual, is used to translate one or two different input frequencies greater than 1 MHz to one of two different output frequencies between 77.76 and 805.6641 MHz, All the major FEC rates are supported such as 15/14 ths and 255/237. Fout =77.76-805.6641 MHz, T(rise/fall) =250 ps, duty cycle =49/51%, jitter =0.23 ps rms, input Fr tracking capability >40 ppm, supply voltage =3.3 V @ 135 mA, size =1.2"xl.0"x0.25" mm, 0 to +70C, -40 to +85C
22758 Frequency translator, low jitter PECL output, accepts multiple input frequencies up to 170 MHz, locked to a specific input frequency, eg 8 kHz, lock/loss of signal alarm. Fout =77.76-170 MHz, T(rise/fall) =0.5 ns, duty cycle =45/55%, jitter <0.5 ps rms, input Fr tracking capability >40 ppm, supply voltage =5.0 or 3.3 V @ 75-45 mA, 0 to +70C, -40 to +85C, size =25.4x20.32x6.35 mm
22759 Frequency translator, optional HCMOS or PECL output, low output jitter, accepts multiple input frequencies up to 77.76 MHz, locked to specified input frequency, eg 8 kHz, surface mount package (1"x0.8"x0.2"). Fout =1.544-77.76 MHz, T(rise/fall) =0.5 ns (PECL), 1.4 ns (HCMOS), duty cycle =45/55%, jitter =0.5 ps rms, input Fr tracking capability >50 ppm, supply voltage =5.0 or 3.3 V @ 45 mA, 0 to +70C, -40 to +85C50 ppm, supply voltage =5.0 or 3.3 V @ 45 mA, 0 to +70C, -40 to +85C">
22760 Frequency translator/ clock smoother, is a SAW based clock smoother and frequency translator which is used to "dean up" noisy input signals. This series can accept any PECL or LVDS input signal from 1.024 to 1200 MHz and clean up the signal to provide an ultra low jitter output signal Applications: SONET/SDH, DWDM, ATM, FDM, DSL-PON interconnects, FEC. Fout =77.76-1200 MHz, T(rise/fall) =250 ps, duty cycle =49/51%, jitter =0.23 ps rms, input Fr tracking capability >40 ppm, supply voltage =5.0 & 3.3 V @ 70-65 mA, size =25.4x20.32x6.35 mm, 0 to +70C, -40 to +85C40 ppm, supply voltage =5.0 & 3.3 V @ 70-65 mA, size =25.4x20.32x6.35 mm, 0 to +70C, -40 to +85C">


  
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